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Introduction to DFT
Theory
Introduction to SOC
DFT Basics
Chip Fabrication Process
Quiz
Assignment
Lab
Lab Guide
Introduction to Scan Insertion
Scan Insertion
Theory
Scan Architecture Overview
Scan Design Basics
Scan Golden Rules
ICG and Lockup Latches
Test Protocol DRC
Quiz
Assignment
Lab
Lab Guide
Tool Invoke
Lab Guide
DRC Violation and Fix_DC Commands
Lab Guide
DRC Violation and Fix_Netlist Hack
Lab Guide
Multi Chain Scan Insertion
Scan Compression
Theory
Need for Scan Compression
Scan Compression Architecture
Scan Compression Modes
Hierachical Scan Design, At-speed and OCC
Quiz
Assignment
Lab
Lab Guide
Compression Lab
Lab Guide
Compression Ratio Max Chain
Lab Guide
CTL File Part-1
CTL File Part-2
Lab Guide
OCC Insertion
Boundary Scan
Theory
Motivation for Boundary Scan Architecture
Boundary Scan Design
Joint Test Action Group (JTAG)
IJTAG, BSDL, Standard Embedded Core Test
Quiz
Assignment
Lab
Lab Guide
JTAG Insertion
JTAG Simulation
Introduction to ATPG & ATPG Basics
Theory
Single Stuck at fault
Fault Collapsing
ATPG Algorithm and TetraMAX tool Flow
Quiz
Assignment
Lab
Lab Guide
Introduction to TetraMAX 1A
Introduction to TetraMAX 1B
Lab Guide
Scan Blockage DRC Analysis
DRC Fix
Pattern Generation
Fault Models
Theory
Fault Models, Single Stuck at Operation
Delay Fault Model
At speed Testing
MCP, False path and Bridging Fault Models
ATPG Types
Quiz
Assignment
Lab
Lab Guide
Transition Delay ATPG pattern generation
Stuck-at Scan compression pattern generation
Path Delay ATPG pattern generation
Fault Classes
Theory
ATPG DRC Rules
Fault Classes
ATPG Effectiveness
ATPG Modes
TetraMAX ATPG Flow
Coverage Improvement Techniques
Quiz
Assignment
ATPG Simulation
Theory
Simulation and Simulation Types
Gate Level Simulation
Simulation Failure
Quiz
Assignment
Lab
Lab Guide
Chain Pattern Simulation & Scan Pattern Simulation
Pattern Simulation Failure Debugging, Scan Insertion ATPG and Pattern Simulation
Lab Guide
Stuck-at ATPG chain pattern simulation
Stuck-at ATPG scan pattern simulation
Stuck-at ATPG pattern simulation failure debugging
Scan insertion, ATPG and Pattern simulation
Timing simulation Lab
Simulation mismatch
ATPG Diagnosis
Theory
ATPG Diagnosis
Quiz
Assignment
Lab
Lab Guide
ATPG Coverage
Diagnosis
Built In Self Test (BIST)
Theory
Introduction to BIST
Quiz
Assignment
Project
Architectural Document
Problem Statement
Project Video