Introduction to DFT:

This Course will enlighten the learners about scan design for testing or Design for Testability. The learners will get an idea about the role of DFT Engineers in each stage of chip life cycle. Also gives an introduction to what DFT is, and why it is needed.

Scan Insertion without Compression:

This Course will enlighten the learners about scan design for testing or Design for Testability. The learners will get an idea about the role of DFT Engineers in each stage of chip life cycle. Also gives an introduction to what DFT is, and why it is needed.

 This course talks about detailed concepts on Scan Insertion, and Scan Design Rules with suitable examples. This course will give in-depth details on Lockup Latches.

Scan Insertion and Scan Compression with OCC:

This Course will enlighten the learners about scan design for testing or Design for Testability. The learners will get an idea about the role of DFT Engineers in each stage of chip life cycle. Also gives an introduction to what DFT is, and why it is needed.

 This course talks about detailed concepts on Scan Insertion, and Scan Design Rules with suitable examples. This course will give in-depth details on Lockup Latches.

You will also learn how to reduce the test application time, test data volume, and thereby test cost of an IC due to the increase in size and complexity with the concept of scan compression. The concepts of OCC is also discussed in this course.

Boundary Scan:

This course gives insights about detailed concepts on, JTAG, Boundary Scan and IJTAG and also penetrates in-depth on details of IEEE1149.1, IEEE 1687 and IEEE P1500.

You will also learn about how JTAG TAP state machine operates and how it is used to do connectivity test between multiple chips in Printed Circuit Board. The IJTAG operation, ICL and PDL concepts are also discussed in this course.

Automatic Test Pattern Generation (ATPG)

This course will help the learners to understand how the tool generates optimized patterns by only considering a subset of faults and thereby covering the entire fault in the design.​They will also understand the rules which will help to get the optimized patterns.

You will also understand about the different structural level fault models, in-depth knowledge about the delay fault models and different approaches to test them.​ Different ATPG DRC rules, deep knowledge about different Fault classes in ATPG Tool, and different coverage improvement techniques will be discussed in this course.

Will also get in-depth knowledge about different ATPG Modes, TetraMAX Tool Flow, etc.​ And also understand the different stages involved in the simulation process and different simulation approaches​, simulation with and without timing, causes for simulation Failure, and Fault simulation​The basics of ATPG diagnosis like the necessity of diagnosis in post-silicon and its challenges​, diagnosis flow and various input files required for diagnosis​ stage are also covered.

​Introduction to BIST

In this course you will understand about the concept of BIST, its architecture, motivation for BIST than normal Scan methodology​. You will also get insights about LBIST and MBIST methodologies, various algorithms, and memory fault types​.