Preview Verilog for Design and Verification

Language Introduction

Module, Module Instantiation, Procedural Statement and Test Bench

Quiz

Assignment

Data Types and Operators

Lexical Elements, Registers, Nets and Operators

Quiz

Assignment

Sequential Circuit Modelling

Arrays, System Tasks & Functions, Procedural Assignments

Quiz

Assignment

Procedural Timing Controls & Conditional Statements

Race Conditions, Timing Control, Block Statements, Conditional & Loop Statements

Quiz

Assignment

Tasks and Functions

Tasks ,Functions ,Q&A

Quiz

Assignment