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Introduction to Design Verification and System Verilog
Theory
Introduction to the ChipEdge Verification Course
ASIC Verification Flow
Levels of Verification and Common Acronyms-
Testbench Architecture
Verilog vs SystemVerilog
Upcoming Topics
Quiz
Assignment
Lab
Verdi Tool Introduction
System Verilog Datatypes
Theory
Introduction to SV Datatypes
Advantages of SV Datatypes
Logic Datatype
Value-Set in Verilog vs SV and 2 State vs 4 State Variables
Arrays
Structures and Unions
String Datatypes
Enumerated and event datatypes
Quiz
Assignment
Lab
Lab Guide
Lab Assignment
Lab Solution
System Verilog Interfaces
Theory
Inter module communication using ports vs interfaces
Specific Interface Ports
Refering Interface signals and methods
Interface Process and Methods
Virtual interface
Clocking Block
Clock Skew and it's declaration
Clocking Blocks as timing controls
Quiz
Assigment
Lab
Lab Guide
Lab Assignment
Lab Solution Part-1
Lab Solution Part-2
Lab Solution Part-3
System Verilog OOPs
Theory
SystemVerilog and OOPs
SystemVerilog Class
Inheritance
this and super operator
Shallow Copy and Deep Copy
Parameterized and typedef classes​​
Polymorphism
Abstract Class
Encapsulation
Dynamic Casting
Scope resolution operator
Quiz
Assignment
Lab
Lab Guide
Lab Assignment
Lab Solution
Randomization
Theory
Directed vs. Random Testing_
Constrained Random Verification
Randomization Basics ​
Specifying Constraints
Computing the Solution Space
Constraint Performance Tips
Random Stability
Random Sequences and Case​
Quiz
Module_5 Assignment
Lab
Lab Guide
Lab Assignment
Lab Solution
Inter-Process Communication
Theory
SystemVerilog threads
Event
Mailbox and it's Initialization
Parameterized Mailboxes
Mailbox Methods
Introduction to Semaphores
Semaphore Keys
Quiz
Assignment
Lab
Lab Guide
Lab Assignment
Lab Solution
Assertions
Theory
Verilog and SV Event regions
Program Block
Introduction to Assertions
Advantages of Assertions
Types of Assertions
Sequence and Property
Writing Assertion Sequence Using operators
Writing Assertion System Tasks
SVA Tips
Quiz
Assignment
Lab
Lab Guide
Lab Assignment
Lab Solution
Coverage
Theory
Introduction To Coverage
Code coverage
Functional Coverage
SV for Functional Coverage
Cover Groups & Cover Points
Cover Bins & Cross coverage Constructs
Coverage Options & Methods
SV Additional Topics
Quiz
Assignment
Lab
Lab Guide
Lab Assignment
Lab Solution
Introduction to UVM
Limitation of SV Testbench
Evolution of UVM
Features of UVM
UVM Class Hierarchy
UVM Phases
Factory Registration
TLM
RAL
Quiz
Assignment
UVM Phases
Motivation for Phases in UVM
UVM Phases Categorization
Built Time Phases
Run Time Phases
Clean Up Phases
Reporting mechanism
Quiz
Assignment
UVM- Transaction Level Modelling (TLM)
Introduction to TLM
Ports, exports, implementation
Analysis ports
TLM FIFO
Hierarchical Connections
Example of TLM Connections
TLM Implementation Ports Declaration Macros
TLM 2.0
Quiz
Assignment
UVM- Factory Registration and Methods
Introduction to Factory
Factory Registration
UVM Field Macros
Factory Methods
Create Methods
Factory Override
Quiz
Assignment
UVM- Construction of Universal Verification Components
Virtual Interface
UVM Config & Resource Database
Construction of UVC
Generating Sequences
Sequence Drive Communication
Quiz
Assignment
UVM- Register Abstraction Layer(RAL)
Introduction to RAL
Register Model Building Block Classes
Register Model in UVM Env
Access API
Frontdoor and Backdoor Access
Quiz
Assignment
UVM- Advanced Concepts
Virtual Sequence and Virtual Sequencer
UVM Callbacks
UVM Event
UVM Barrier
UVM Heartbeat
Commonly used Command line Switches
Quiz
Assignment
Universal Verification Methodology (UVM)- Lab
Lab Guide
Lab Assignment
Lab Solution Part-1
Lab Solution Part-2
Advanced Peripheral Bus Protocol (APB)
Theory
APB Protocol
Lab-SV Based Verification
Lab Guide
SV Solution Part 1
SV Solution Part 2
Lab- UVM Based Verification
Lab Guide
UVM Solution Part 1
UVM Solution Part 2
UVM Solution Part 3
Advanced eXtensible Interface (AXI) 4 -Lite
Theory
AXI4- LITE
Lab
Part 1
Part 2
Part 3
Part 4
Part 5